Search - crc verilog

[Communication] crc上传程序

Description: 写CRC编解码程序时，整理的文件，压缩文件既有理论说明，也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
Platform: | Size: 706776 | Author: cdl | Hits:

[Other resource] crc

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用verilog HDL编写
Platform: | Size: 819 | Author: 宋子奇 | Hits:

[Other resource] fast-crc.tar

Description: 一个verilog实现的crc校验，用于fpga实现，快速，准确有效
Platform: | Size: 1440278 | Author: 枫叶鹏 | Hits:

[Other resource] crc

Description: 用Verilog编写crc校验码，包括8位，12位，16位，32位，非常实用
Platform: | Size: 11138 | Author: asd | Hits:

[Crack Hack] crc

Description: 用于10M，100M，1000M以太网的并行CRC算法，有别于一般的CRC算法。verilog描述
Platform: | Size: 1469 | Author: winwalk | Hits:

[Other resource] crc

Description: rfid中crc模块的verilog代码
Platform: | Size: 1056 | Author: yan zeng | Hits:

[Other resource] CRC

Description: verilog 实现循环冗余校验源代码
Platform: | Size: 367681 | Author: 长空 | Hits:

[VHDL-FPGA-Verilog] pcm_verilog

Description: 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
Platform: | Size: 47104 | Author: way | Hits:

[Windows Develop] crc_wizard_v1_1

Description: 用Verilog写的CRC校验程序非常不错-Written using Verilog procedures are very good CRC Checksum
Platform: | Size: 486400 | Author: westspeed | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
Platform: | Size: 1024 | Author: 刘彻 | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
Platform: | Size: 934912 | Author: sunlee | Hits:

[Crack Hack] crc1

Description: CRC编码verilog代码，用于实现crc编码功能-CRC coding Verilog code for CRC encoding capabilities to achieve
Platform: | Size: 1024 | Author: 龙一 | Hits:

[VHDL-FPGA-Verilog] example

Description: FPGA大量实例,仅供参考,适合新手学习-FPGA a large number of examples for reference only, suitable for novices to learn
Platform: | Size: 2601984 | Author: Sem | Hits:

[VHDL-FPGA-Verilog] CRC_32

Description: 用verilog语言实现的的的32位CRC生成与检验的代码-The 32bits CRC using hardware describe language of verilog
Platform: | Size: 1024 | Author: 朱猪 | Hits:

[Books] Xmodem

Description: 用 UART 做文件传输（采用 Xmodem协议）.pdf-Xmodem Protol
Platform: | Size: 506880 | Author: 王晓斌 | Hits:

[Other] uvm-crc-test

Description: UVM简单例程，DUT为Verilog小程序。(UVM simple routine, DUT is Verilog applet.)
Platform: | Size: 5120 | Author: wenxulyu | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 包括下面文档： readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.(Contains the following files readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.)
Platform: | Size: 10240 | Author: chris_lj | Hits:

[VHDL-FPGA-Verilog] crc_nguyenquanicd

Description: design crc module in data network transmission
Platform: | Size: 2048 | Author: Zick | Hits:

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

Description: Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
Platform: | Size: 167936 | Author: 三棵树机务段 | Hits:

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[Communication] crc上传程序

[Other resource] crc

[Other resource] fast-crc.tar

[Other resource] crc

[Crack Hack] crc

[Other resource] crc

[Other resource] CRC

[VHDL-FPGA-Verilog] pcm_verilog

[Windows Develop] crc_wizard_v1_1

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

[Communication] crc_verilog

[VHDL-FPGA-Verilog] ethernet.tar

[Crack Hack] crc1

[VHDL-FPGA-Verilog] example

[VHDL-FPGA-Verilog] CRC_32

[Books] Xmodem

[Other] uvm-crc-test

[VHDL-FPGA-Verilog] crc_verilog_xilinx

[VHDL-FPGA-Verilog] crc_nguyenquanicd

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

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